The present invention relates to a data processor for executing an exception handling program to cope with the occurrence of exceptions such as reset event, exception events and interrupt events. More specifically, the invention relates to technology for shortening the time required for the transition from a moment of occurrence of an exception event to the operation of an exception handler for coping with the exception event. The invention relates to technology that can be effectively adapted to, for example, a single-chip microcomputer or a microprocessor contained in a memory management unit (MMU).
In processing the data using a central processing unit that is included in the data processor, there may often occur general exception events such as decoding of undefined instruction in an instruction set of the data processor, invalid arithmetic operation, protection violation in a virtual storage, TLB miss exception events, etc., as well as end signaling for informing the central processing unit of the end of data input/output operation in the peripheral circuits of the data processor and interrupt requests (referred to as general interrupt events) such as request of reception from a communication module in the data processor.
When exception events such as the above-mentioned general exception events and general interrupt events occur, the central processing unit suspends the execution of instructions of a data processing program, shifts the control to an exception handler to cope with exceptions that have occurred, executes the data processing specified by the exception handler, and works to cope with the exception events. After the exception handler is executed, the central processing unit retries the suspended instruction or returns to an instruction address next to the suspended instruction, and resumes the suspended data processing program. Therefore, if general exception events and general interrupt events occur, the central processing unit executes the operation to save values of a program counter therein and internal conditions of the status register into the stack regions of an external memory. When the processing of the central processing unit returns from the exception handler to the suspended data processing program, the central processing unit transfers the values saved in the program counter and the internal conditions of the status register from the stack regions of the external memory to the program counter and to the status register, respectively, and continues the suspended data processing program.
A predetermined data processing program has been branched to a predetermined exception handler by a method of fixing a variety of destination addresses (head memory addresses of a variety of exception handlers) using a hardware (logic circuit) or by a vector system which designates destination addresses from the central processing unit. According to the vector system, for example, a vector table storing head addresses of a variety of exception handlers for responding to an interrupt request is arranged on an external memory, a pointer (interrupt vector register) of the vector table is designated from the central processing unit, the head address of a corresponding exception handler is read out from the designated vector table, and a desired exception handler is read out from a position of the head address that is read out and is executed.
As a literature describing exception events such as interrupt requests, there can be cited xe2x80x9cMICROCOMPUTER HANDBOOKxe2x80x9d, Ohm Co., Dec. 25, 1987, pp. 177-178.
The above-mentioned vector system, however, requires the operation for reading the external memory to obtain a head address of a corresponding exception handler from the vector table from the occurrence of an exception event up to dealing with it. Therefore, the time required for the transition from the occurrence of the exception event to the branching to a corresponding handler increases by the amount of operation for reading the external memory. Moreover, when the data in the program counter, in the status register and in the general-purpose register are to be saved to the stack regions of the external memory prior to branching to a corresponding exception handler, response to the exception event is delayed even by the operation for writing data into the external memory.
In particular, a quick response to an exception event, related to TLB miss exception event that occurs in synchronism with the operation of the central processing unit, means that the time can be shortened from the moment of occurrence of TLB miss exception event to the retry of the suspended instruction. The present inventors have discovered that this is quite important for enhancing data processing performance of the central processing unit. This is because, though it is classified as an exception event, the TLB miss exception event is an event that usually occurs during the execution of a data processing program free from mistake and is substantially different from exception events that occur due to a mistake involved in the data processing program prepared by a user. Therefore, to quickly cope with TLB miss exception events is to improve data processing performance of the central processing unit.
A method can be further contrived to completely fix a variety of destination addresses by hardware. However, this method is little versatile for mapping the exception handlers related to the user description or for the program sizes, and is little convenient to use. It is further considered that the amount of hardware increases for forming destination addresses.
The object of the present invention is to provide a data processor which is capable of shortening a transition time of from the moment of occurrence of an exception event up to shifting or branching the processing into an exception handler for coping with it.
Another object of the present invention is to provide a data processor which is capable of providing the constitution of exception handler with freedom to respond to exception events.
A further object of the present invention is to provide a data processor which is capable of shortening the transition time for a processing such as of a TLB miss exception event which can make it possible to execute the data processing at high speeds, and is also capable of offering high degree of versatility for the mapping of exception handlers on the memory and for the memory sizes of the exception handlers concerning those exception events and interrupt events which may not much contribute to executing the data processing at high speeds so much as the TLB miss exception events.
A still further object of the present invention is to provide a low-cost and high-speed data processor capable of satisfying both contracting the physical circuit scale from the standpoint of handling exception events and executing the data processing at high speeds.
The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
Among the inventions disclosed in this application, representative examples will now be briefly described below.
Referring to FIG. 1, a single-chip data processor comprises:
a storage circuit (EXPEVT, INTEVT) into which, in response to an exception event, an exception code assigned in advance to it (such as reset event, general exception events, general interrupt requests) is stored; and
a central processing unit (CPU) including a program counter (PC), and a control means (CTRL) which, in response to an exception event, writes a predetermined instruction address into said program counter so that a first exception handler assigned to said instruction address may be executed.
In accordance with a processing specified in the first exception handler, the control means calculates a second instruction address for branching into a second exception handler from the first exception handler by utilizing the exception code written into the storage circuit as an address offset, and sets the obtained second instruction address to the program counter.
Branching into the predetermined instruction address is, for example, carried out by operating a vector point that is obtained by hardware as shown in FIG. 2. As shown in FIG. 2, a first exception handler assigned to the predetermined instruction address (vector point at a destination) is an exception handler for a TLB miss exception event which is a general exception event specific to the vector point, is a common exception handler for a plurality of general exception events (e.g., a plurality of general exception events other than TLB miss exception events) specific to the vector point, or is a common exception handler for a plurality of interrupt events. In the common exception handler, the above-mentioned exception code is utilized as an address offset for branching into another exception handler (second exception handler) specific to individual exceptions. A base address for the exception code (address offset) is determined by the description of the common exception handler. The base address may be, for example, VBR (value of vector base register)+Hxe2x80x2100 (symbol Hxe2x80x2 means hexadecimal notation), or a value of the program counter at the time of branching, or a value obtained through a suitable calculation.
From another point of view, the single-chip data processor possesses vector offsets which are fixed offsets for the vector base addresses in a number smaller than the number of exception events in order to change the order of executing instructions by the central processing unit depending upon the occurrence of exception events.
A single-chip data processor according to the present invention comprises a first saved register (SSR) in which internal conditions of a status register are stored when an exception event occurs, and a second saved register (SPC) which stores a return instruction address corresponding to an instruction stored in said program counter and to be executed after the return from the exception handling. Employment of the first and second saved registers makes it possible to decrease the number of times of access to the external memory for saving the internal conditions of the status register and return instruction addresses.
According to the present invention, furthermore, the central processing unit in the single-chip data processor includes an arithmetic and logic operation circuit (ALU), a constant generating unit or an operation means (CVG, SFT) which generates a predetermined value (vector offset) in response to the occurrence of an exception event, and a base register (VBR) for storing base addresses of a plurality of exception handlers stored in an external memory, and operates a vector point obtained by hardware shown in FIG. 2. Being controlled by the control circuit, the arithmetic and logic operation circuit adds a base address and a predetermined value together to generate a predetermined instruction address (destination instruction address). According to FIG. 2, for instance, vector offsets of general exception events other than the TLB miss exception events are denoted by Hxe2x80x2100, and vector offsets of the TLB miss exception events are denoted by Hxe2x80x2400. The constant-generating unit is constituted by a constant-generating circuit (CVG) that generates a constant value of two bits and a shifting circuit (SFT) that shifts by a predetermined amount the constant value of two bits output from the constant-generating circuit, featuring a simplified circuit constitution.
The register which is a storage circuit for storing exception codes is constituted of a first register (EXPEVT) assigned to first exception events (e.g., general exception events) that occur in synchronism with the operation of the central processing unit (CPU) and a second register (INTEVT) assigned to second exception events (e.g., interrupt events) that occur out of synchronism with the operation of the central processing unit. The reset event is included in the group of second exception events.
The status register (SR) includes a first control bit (MD) which decides whether the single-chip data processor is in a user state in which a user program is running or a supervisor state in which a system program is running, and a second control bit (BL) which decides whether to accept other exception events that follow the above-mentioned exception events.
The control means saves the internal conditions and the restored instruction addresses in the first saved register (SSR) and in the second saved register (SPC), respectively, and then sets to the first control bit the data representing the supervisor state, sets to the second control bit the data indicating that the other exception events that follow the above-mentioned exception events should be masked, and branches the processing to the first exception handler assigned to the predetermined instruction address. Access to the first and second control bits is accomplished relying upon a predetermined supervisor instruction (e.g., LDC, STC).
That is, as shown in FIG. 2, the processor mode on the first exception handler assigned to the vector point is in a supervisor state masking multiple acceptance of exception events. Here, the supervisor state is different from the user state in regard to that the supervisor state makes it possible to access to address space which in the user state could be an address error as well as to execute a supervisor instruction (e.g., LDC, STC) that cannot be executed in the user state.
In order that the internal conditions and the return address can be saved in the first and second saved registers when an exception event occurs, it is determined whether multiple acceptance of new exception events should be masked or not on the first exception handler assigned to the vector point, and the content thereof is reflected on the control bit. When multiple exception events are to be accepted, the contents of the first and second saved registers are saved in the memory.
In order to decrease the frequency of saving the content of the general-purpose register in the memory when an exception event occurs or to increase the degree of freedom of processing for the general-purpose register, there are provided first and second general-purpose register sets to constitute a plurality of banks. One of the first and second general-purpose register sets is used as general-purpose registers in the supervisor state, and the other one of the first and second general-purpose register sets is used as general-purpose registers in the user state. It is desired that the register banks of the general-purpose registers are changed over by software in the supervisor state only.
According to the present invention, the single-chip data processor further has an instruction break controller (UBC). The instruction break controller (UBC) includes an instruction break address register (IBR) to which a break point address is set, and generates an instruction break exception event when an instruction corresponding to the instruction address that is set to the instruction break address register is executed by the central processing unit. When the instruction break exception is detected in a state where it is instructed to mask the acceptance of multiple exception events, the control means does not save the internal conditions and the return instruction address in the first and second saved registers but branches the processing to the instruction break exception handler. The instruction break exception handler saves the above-mentioned conditions and the contents of the saved register for saving return address in the memory, calculates the return instruction address from the instruction break exception handler by utilizing a break point address held by the instruction break address register, and writes the return instruction address that is calculated into the second saved register. Thus, the instruction break exception event is processed by the exception handler in a state where multiple acceptance of the exception events has been masked.
In the state of masking the multiple acceptance of exception events, furthermore, when a first exception event other than the instruction break exception event is detected, the control means records the exception code thereof into the exception register and then branches the processing to a reset exception handler. When a second exception event is detected, furthermore, the control means masks the acceptance of the second exception event until the state of masking the multiple acceptance of exception events is reset.
The following effects are obtained from the above-mentioned means.
The first exception handler to which the vector point is assigned is regarded, for given exception events (e.g., TLB miss exception events), to be an exception handler specific thereto and is regarded, for other exception factors (e.g., general exception events other than TLB miss exception events), to be a common exception handler including a description for branching to a second exception handler (e.g., address error exception events, TLB protect violation exception events) which is a separate exception handler provided for each of the factors.
In the former case, branching is accomplished to a particular first exception handler relying only upon the processing by hardware without accompanied by memory access, and the process can be shifted to a desired exception processing at a high speed. In the latter case, the address of a destination can be obtained without accessing the address table on the memory since an exception code of a memory circuit (exception register) is utilized as an address offset for branching to another handler, and the same effects can be obtained.
From another point of view, the exception code held in the exception register in the latter case is so assigned as can be utilized as an address offset for branching to a further exception handler. For instance, the codes are assigned maintaining a gap of Hxe2x80x220 that corresponds to 32 bytes reckoned as addresses.
In the latter case, furthermore, the exception code is utilized as an address offset for branching. Accordingly, the base address for the above offset can be freely determined according to description of the first exception handler assigned to the vector point determined by hardware, making it possible to guarantee the degree of freedom for the practical address of destination or for the size of the exception handler at the destination.
Employment of the register (SSR, SPC) for saving the internal conditions and return instruction address, decreases the memory access during the saving when an exception event has occurred.
When the operation clocks of the central processing unit has a multiple of the frequency of the operation clocks of peripheral modules which are regarded to be sources of generating interrupt events, registers for storing exception codes are provided for the first exception events generated in synchronism with the operation of the central processing unit and for the second exception events generated out of synchronism therewith, to cope with both the general exception events which are the first exception events and the interrupt events which are the second exception events. This is to avoid complex processing for writing exception codes into a common register at similar timings for the occurrence of the two exception events.
By setting the initial processor mode on the handler at a destination (first exception handler) determined by hardware depending upon the exception events, to be constant relying upon the state of masking multiple acceptance of exception events and upon the supervisor state, it is allowed to guarantee a high degree of freedom for the content of exception handling specified by the user on the handler.
With the register banks of the general-purpose registers being allowed to be changed over by software only in the supervisor state, it is allowed to utilize in the supervisor state a general-purpose register of a bank which is different from that of the user state. When, for example, the processor mode is changed over from the user state to the supervisor state in the exception event processing, the content of the general-purpose register need not be saved in the memory, and the processing can be shifted at a high speed to the exception event processing.
With the instruction break exception events being processed in the exception handler in a state of masking exception events, it is allowed to evaluate the system or to debug the program by applying instruction break at any position even for the programs that are to be debugged in the state where acceptance of multiple exception events is masked.